The invention relates to electrical counters and more particularly to those that count in other than binary code.
Previous electrical counters (for counting a series of electrical pulses applied to them) have generally counted in binary code of 00, 01, 10, 11 and 00 (for a 2 bit counter) on succeeding pulses to be counted by the counter. If more than one such 2 bit counter is utilized for providing a successive change in value of a succeeding counter stage, so that the value 100 may be registered for example, it is necessary that the outputs of the two latches or memory devices in the first stage holding the values of 11 shall be ANDed together for the purpose. When more than three values of count, such as for a count of 110100, etc. are needed, the outputs of all of the previous latches must be ANDed together at the same time for the purpose. This has led to a complexity of circuitry.